systba_topology
2017-04-01 10:24:09 3 举报AI智能生成
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uvm structure
作者其他创作
大纲/内容
test_top
sys_env
subsys_env_hash(ap/aon...)
uvc_env_hash(mst/slv)
agent
driver
inst
monitor
meminst
reginst
seqr
hdl_path
is_active
cfg
scb_adapter
ed_addr_export
ed_burst_export
outport
st_burst_export
scoreboard
uvm_analysis_imp_expect
uvm_analysis_imp_insert
systba_cov_base
reg_model(uvm_config_db::get)
sys_vseqr
rsp_export
seq_item_export
arb_queue
lock_queue
num_last_reqs
num_last_resps
m_resource_hash
spec_load
reg_model(uvm_config_db::set)
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