iregfile_out_type : record
data1: std_logic_vector(31 downto 0)data2: std_logic_vector(31 downto 0)
iregfile_in : record
raddr1: std_logic_vector(4 downto 0)raddr2: std_logic_vector(4 downto 0)waddr: std_logic_vector(4 downto 0)wdata: std_logic_vector(31 downto 0) ren1: std_logic\t\t\t ren2: std_logic\t\t\twren: std_logic
registers : record
f: fetch_reg_typed: decode_reg_typee: execute_reg_typem: memory_reg_typew: write_reg_type
word : std_logic_vector(31 downto 0)
rfatype : std_logic_vector(4 downto 0)
execute_reg_type : record
rd: rfatypewreg: std_logic rfe1: std_logic rfe2: std_logic rfa1: rfatype rfa2: rfatype reg1: word reg2: word imm: word cnt: std_logic_vector(1 downto 0); aluop: std_logic_vector(7 downto 0) alusel: std_logic_vector(2 downto 0)inst_valid: std_logichilo: std_logic_vector(63 downto 0)
memory_reg_type : record
waddr: rfatype wreg: std_logic result: word whilo: std_logic hilo: std_logic_vector(63 downto 0)
write_reg_type : record
result: wordwaddr: rfatypewreg: std_logicwhilo: std_logichilo: std_logic_vector(63 downto 0)
decode_reg_type : record
pc: pctypeinst: word
fetch_reg_type : record
pc: pctype
pctype : std_logic_vector(31 downto 2)
