core gate level netlist
Hierrahcial DFT flow
RTL
6. pattern retargeting
4. Scan insertion （edt_mode）
top gate level netlist
5. retargetable ATPGpattern generation
core level external mode pattern
Core level
1. Mbist insertion
RTL with mbist
top level test pattern
5. ATPGpattern generation
3. Synthesis
core scan inserted netlist
2. EDT+OCC+Lbist+SSN insertion
4. Scan insertion （internal/exetrnalmode）
Top level
2. EDT+OCC+Lbist+SSN+Mission mode insertion
1. Boundary Scan+Mbist insertion
retargeted test pattern
top scan inserted netlist
core level internal mode pattern
