pipeline cpu
2023-08-02 14:27:42 0 举报登录查看完整内容
流水线cpu原理图，采用哈佛结构，实现MIPS指令集中的20个左右的指令
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大纲/内容
reg1_data[31:0]
id_inst_o[31:0]
data_ram_wen
ctrl
id_branch_flag_o
reg2_addr[31:0]
reg1_read[31:0]
ex_reg1_i[31:0]
mem_aluop_i[4:0]
new_pc[31:0]
ex_wreg_o
wb_wdata_i[31:0]
mem_wreg_i
id_wreg__o
mem_mem_addr_i[31:0]
rstn
stall[5:0]
ex_wd_o[4:0]
inst_rom_data[31:0]
reg2_read[31:0]
data_ram
ex
id_inst_i[31:0]
id_reg1_op[31:0]
data_ram_addr[31:0]
mem_wdata_i[31:0]
data_ram_wdata[31:0]
wb_wreg_i
mem
clk
regfile
mem_wd_i[4:0]
ex_aluop_o[4:0]
ex_wd_i
ex_mem_addr_o[31:0]
id_wd_o[4:0]
if_id
mem_wreg_o
wb_wd_i[4:0]
stallreq_from_id
id_reg2_op[31:0]
pc_reg
id_aluop_o[4:0]
flush
id_pc_i[31:0]
ex_reg2_o[31:0]
data_ram_rdata[31:0]
mem_wb
ex_reg2_i[31:0]
mem_wd_o[4:0]
mem_reg2_i[31:0]
reg2_data[31:0]
id
reg1_addr[31:0]
inst_rom
mem_wdata_o[31:0]
id_ex
ex_wreg_i
id_branch_target_addr_o[31:0]
ex_aluop_i[4:0]
ex_wdata_o[31:0]
ex_mem
pc[31:0]
ex_inst_i[31:0]
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