框图
2025-08-13 19:04:36 0 举报框图
作者其他创作
大纲/内容
XSTileWrap
Jtag_clk-50MHz
Decoupled intf
kmh_wrapper
sync_dff_ip
cpu_clk
noc_clk
ICG
jtag_clk
noc_clk:1.5GHz
Vld & data[63:0]
Int(i_core0_ms_int/i_core0_mt_int)
dmInner
Async intf
Sync intf
Chi Async_bridge_src
XSTop
Chi Async_bridge_sink
dmoOuter
dtm
prog
chi
Imsic_map
Data rate:100MHz
TL
imsic_bus
XSTile
syscnt_sync
Decouple
Cpu_clk-2.5GHz
span style=\"font-size:14px; font-family:SimSun; color:#000000; letter-spacing:0px;\
Always on
Always on power domain
KMH power domain
0 条评论
下一页
